1. Filed of the Invention
The present invention relates to a semiconductor device requiring a high level integration such as dynamic RAMs (DRAMs) and a manufacturing method thereof, and more particularly, a semiconductor device having a structure for realizing a good electric connection between an buried conductor and a semiconductor region and a manufacturing method thereof.
2. Description of the Related Art
In recent years, semiconductor integrated circuits are integrated in larger and larger scale and, more particularly, DRAMs having a high integration by giga bits are demanded. According to such higher integration of semiconductors, the semiconductor devices are developed into three-dimensional structure from two-dimensional structure as before and a technology for obtaining a contact region substantially equal to or higher than the conventional one are adopted there to within a projective region smaller in two-dimensional plane than before. Usually, the DRAM memory cell of one transistor cell design is composed of a charge storage capacitor section defined in a semiconductor substrate or in an interlayer insulation film and an access transistor connected to this charge storage capacitor section. As the memory cell is made smaller, the structure of a connection section between a main electrode region of the access transistor and the charge storage capacitor section is realized smaller. In this situation, many modifications are proposed for the structure of this connection section and the manufacturing process thereof.
Now, the problems of the substrate contact of the conventional DRAM will be described in respect of a connection section between the charge storage capacitor section and the source region of the access transistor as follows.
FIG. 1 is a cross-section views of a part of memory cell section of a DRAM. A access transistor comprising an n.sup.+ source region 61 and an n.sup.+ drain region 62 is disposed on a p.sup.- well 52. Moreover, at the left of the n.sup.+ source region 61, one conductor 55 as one electrode of the charge storage capacitor section (trench capacitor), partially not illustrated, and another conductor 56 above it are situated as same electrode, and the n.sup.+ source region 61 and the trench capacitor are electrically connected by an n.sup.+ buried contact 69. Further, to insulate with other memory cell access transistor, an isolation insulation film 2 (STI region) is disposed around each memory cell (a part thereof is shown at the left of the charge storage capacitor section in FIG. 1). The n.sup.+ drain region 62 and a bit line 92 are mutually connected through a contact plug 12. In this structure, the n.sup.+ buried contact 69 and the p.sup.- well 52 are reverse biased to prevent current flow.
However, according to the study of the inventors, a leakage current has sometimes produced near the n.sup.+ buried contact 69. The generation of this leakage current lets the electric charge accumulated in the charge storage capacitor section run into the n.sup.+ drain region 62 despite opening/closing of the access transistor and results in a malfunction. Therefore, the inventors have studied in detail the cause of this leakage current. As the result, we have found that the cause of leakage current near the n.sup.+ buried contact 69 is the fact that a crystal defect 202 is produced at and near the n.sup.+ buried contact 69, and a leakage current has been produced along this crystal defect.
The observation of etch pits or scanning electron microscope (SEM) observation or the like shows that the crystal defect 202 appears at the buried contact 69 and extends to the p.sup.- well 52. A crystal defect 201 generates also at the conductor 56. They show also that the defect appeared in the buried contact 69 is formed continuously from the crystal defect 201 appeared in the conductor 56. Even when this crystal defect 202 does not attain an interface between the buried contact 69 and the p.sup.- well 52, it may provoke leakage current when it attains only an depletion region in the buried contact 69. Note that the measurement of this leakage current allows to screen the fault of a semiconductor device. As the defect, causing such leakage current, only appears and grows by a heat treatment more than 900.degree. C., a semiconductor screening before shipment to the market allows to prevent the defect appearing in the market.
Now the formation steps of such defect will be described according to the manufacturing process. As the conductor 56 during the formation is amorphous (a-Si), crystal defect is absent. The crystal defect does not exists at the p.sup.- well 52 in the buried contact 69, too. Here, the conductor 56 crystallizes by repeating several times a heat treatment of about 900.degree. C. to form the buried contact 69, to form a gate oxide film, to activate or reflow the n.sup.+ source region 61 or the like. This crystallization, beginning from the interface between the a-Si 56 (conductor) and the silicon (buried contact) 69, develops so as to grow epitaxialy towards the inside of the conductor 56. According to the crystallization of the a-Si 56, the internal stress of the conductor increases so as to relieve, resulting in the formation of a crystal defect 201 in the conductor 56. The internal stress will be propagated through this crystal defect to the buried contact 69, which has served as substrate for the epitaxial growth, forming a crystal defect 202. Finally, the crystal defect 202 pierces through the buried contact 69 and attains a p.sup.- well 52.